1. Field of the Invention
This invention relates to buffer-inverter circuits implemented with complementary transistors.
2. Description of the Prior Art
A conventional complementary metal-oxide-silicon (CMOS) address buffer receives a digital input signal having TTL or MOS input potential levels and generates an inverted and a non-inverted output signal, which are complementary signals and have MOS potential levels; see, e.g., FIG. 1. The inverted output signal A is delayed from the input signal by a pair of complementary MOS inverter transistors (T10, T11). This inverted signal (A) is typically inverted a second time to generate a non-inverted output signal A'. Thus there is an additional delay introduced such that the non-inverted output signal at node 16 occurs later in time than the inverted output signal at node 15. This delay is especially significant when the load capacitance (17) connected to the inverted output node (15) is large compared to the input capacitance of the transistors (T12, T13) in the second inverter.
In some applications, it is desirable that the inverted output signal and the non-inverted output signal both change states at essentially the same time. For example, in one type of static random access memory, it is desirable to select one row of memory cells at essentially the same time that another row is de-selected. For this purpose, it is desirable to have a complementary address buffer-inverter in which complementary output signals are generated that both start their transition at the same time, cross through the midway point of their logic swing at essentially the same time and reach the final logic levels at almost the same time. Numerous other applications are also possible.